SH7059 Datasheet, PDF (556/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
Bit
Bit Name Initial Value R/W Description
4
TSR4
0
R
Cycle Counter Overflow Flag
Indicates that the cycle counter has reached its maximum value and is reset
to H'0. Setting CMAX = 0 makes the cycle counter be disabled and TSR4 be
always cleared to 0.
0: Cycle counter has not overflow
Clearing condition: Writing 1 to IRR10 (cycle counter overflow interrupt)
1: Cycle counter has overflow
Setting condition: When the cycle counter value changes from the
maximum value (CMAX) to H'0
3
TSR3
0
R
Timer Compare Match Flag 2
Indicates that a compare-match condition occurred to the timer compare
match register 2 (TCMR2). When the value set in TCMR2 matches the timer
value (TCMR2 = TCNTR), this bit is set. This bit is not set if the TCMR2
value is H'0000. Also, this bit is read-only and is cleared when IRR11 (timer
compare match interrupt 2) is cleared.
0: Timer compare match has not occurred to TCMR2
Clearing condition: Writing 1 to IRR11 (timer compare match interrupt 2)
1: Timer compare match has occurred to TCMR2
Setting condition: TCMR2 matches the timer value (TCMR2 = TCNTR)
2
TSR2
0
R
Timer Compare Match Flag 1
Indicates that a compare-match condition occurred to the timer compare
match register 1 (TCMR1). When the value set in TCMR1 matches the timer
value (TCMR1 = TCNTR), this bit is set. This bit is not set if the TCMR1
value is H'0000. Also, this bit is read-only and is cleared when IRR15 (timer
compare match interrupt 1) is cleared.
0: Timer compare match has not occurred to TCMR1
Clearing condition: Writing 1 to IRR15 (timer compare match interrupt 1)
1: Timer compare match has occurred to TCMR1
Setting condition: TCMR1 matches the timer value (TCMR1 = TCNTR)
1
TSR1
0
R
Timer Compare Match Flag 0
Indicates that a compare-match condition occurred to the timer compare
match register 0 (TCMR0). When the value set in TCMR0 matches the timer
value (TCMR0 = TCNTR), this bit is set. This bit is not set if the TCMR0
value is H'0000. Also, this bit is read-only and is cleared when IRR14 (timer
compare match interrupt 0) is cleared.
0: Timer compare match has not occurred to TCMR0
Clearing condition: Writing 1 to IRR14 (timer compare match interrupt 0)
1: Timer compare match has occurred to TCMR0
Setting condition: TCMR0 matches the timer value (TCMR0 = TCNTR)
0
TSR0
0
R
Timer Overrun Flag
Indicates that the timer has overrun and is reset to H'0000. This bit is set
even when TCMR0 is set to H'FFFF and is enabled to clear the timer value.
0: Timer has not overrun
Clearing condition: Writing 1 to IRR13 (timer overrun interrupt)
1: Timer has overrun
Setting condition: When the timer value changes the value from H'FFFF to
H'0000
Rev.3.00 Mar. 12, 2008 Page 466 of 948
REJ09B0177-0300