SH7059 Datasheet, PDF (373/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
The 32-bit free-running counter (TCNT10A) is an up-counter that performs free-running operations. When input
capture is performed by means of TI10 input, this counter is cleared to H'00000001. When free-running counter
(TCNT10A) reaches the value set in the output compare register (OCR10A), a compare-match interrupt can be
requested.
The input capture register (ICR10A) has an external signal input pin (TI10), and the free-running counter (TCNT10A)
value can be captured by means of input from TI10. Rising edge, falling edge, or both edges can be selected by making
a setting in bits CKEG1 and CKEG0 in the timer control register (TCR10). The TI10 input has a noise canceler
function, which can be enabled by setting the NCE bit in the timer control register (TCR10). When the counter value is
captured, TCNT10A is cleared to 0 and an interrupt can be requested. The captured value can be transferred to the
multiplied clock generation block reload register (RLD10C).
The 8-bit event counter (TCNT10B) is an up-counter that is incremented by TI10 input. When the event counter
(TCNT10B) value reaches the value set in the output compare register (OCR10B), a compare-match interrupt can be
requested. By setting the TRG0DEN bit in the timer control register (TCR10), a capture request can also be issued for
the channel 0 input capture register 0D (ICR0D) when compare-match occurs.
The 8-bit noise canceler counter (TCNT10H) and 8-bit noise canceler compare-match register (NCR10) are used to set
the period for which the noise canceler functions. By setting a value in the noise canceler compare-match register
(TCNT10H) and setting the NCE bit in the timer control register (TCR10), TI10 input is masked when it occurs. At the
same time as TI10 input is masked, the noise canceler counter (TCNT10H) starts counting up on the Pφx10 clock.
When the noise canceler counter (TCNT10H) value matches the noise canceler compare-match register (NCR10)
value, the noise canceler counter (TCNT10H) is cleared to H'0000 and TI10 input masking is cleared.
(2) Multiplied clock generation block
This block has 16-bit reload counters (TCNT10C, RLD10C), a 16-bit register free-running counter (TCNT10G), and a
16-bit general register (GR10G).
16-bit reload counter 10C (RLD10C) is captured by 32-bit input capture register 10A (ICR10A), and when RLDEN in
the timer I/O control register (TIOR10) is 0, the value captured in input capture register 10A is transferred to the
multiplied clock generation block reload register (RLD10C). The value transferred can be selected from 1/32, 1/64,
1/128, or 1/256 the original value, according to the setting of bits PIM1 and PIM0 in TIOR10.
16-bit reload counter 10C (TCNT10C) performs down-count operations. When TCNT10C reaches H'0001, the value is
read automatically from the reload buffer (RLD10C), internal clock AGCK1 is generated, and the down-count
operation is repeated. Internally generated AGCK1 is input as a clock to the multiplied clock correction block 16-bit
correction counter (TCNT10E) and 16-bit free-running counter 10G (TCNT10G).
16-bit register free-running counter 10G (TCNT10G) counts on AGCK1 generated by TCNT10C. It is initialized to
H'0000 by external input from TI10.
The 16-bit general register (GR10G) can be used in a compare-match with free-running counter 10G (TCNT10G) by
setting bits IO10G2 to IO10G0 in the timer I/O control register (TIOR10). An interrupt can be requested when a
compare-match occurs. Also, by setting timer interrupt enable register 10 (TIER10), an interrupt can be request in the
event of TI10 input after a compare-match.
(3) Multiplied clock correction block
This block has three 16-bit correction counters (TCNT10D, TCNT10E, TCNT10F) and a 16-bit correction counter
clear register (TCCLR10). When 32-bit input capture register 10A (ICR10A) performs a capture operation due to input
from external input pin TI10, the value in correction counter 10D (TCNT10D) is transferred to TCNT10E and
TCNT10D is incremented. The value transferred to TCNT10E is 32, 64, 128, or 256 times the TCNT10D value,
according to the setting of bits PIM1 and PIM0 in the timer I/O control register (TIOR10).
16-bit correction counter 10E (TCNT10E) counts up on AGCK1 generated by reload counter 10C (TCNT10C,
RLD10C) in the multiplied clock generation block. However, by setting the CCS bit in the timer I/O control register
(TIOR10), it is possible to stop free-running counter 10E (TCNT10E) when the free-running counter 10D (TCNT10D)
multiplication value specified by PIM1 and PIM0 and the free-running counter 10E (TCNT10E) value match. The
multiplied TCNT10D value is transferred when input capture register 10A (ICR10A) performs a capture operation due
to TI10 input.
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