SH7059 Datasheet, PDF (448/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Serial Communication Interface (SCI)
The transmit data register (TDR) is an 8-bit register that stores data for serial transmission. When the SCI detects that the
transmit shift register (TSR) is empty, it moves transmit data written in TDR into TSR and starts serial transmission.
Continuous serial transmission is possible by writing the next transmit data in TDR during serial transmission from TSR.
The CPU can always read and write to TDR. TDR is initialized to H'FF by a power-on reset, and in hardware standby
mode and software standby mode. It is not initialized by a manual reset.
15.2.5 Serial Mode Register (SMR)
Bit:
7
6
5
C/A
CHR
PE
4
3
2
1
0
O/E
STOP
MP
CKS1
CKS0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The serial mode register (SMR) is an 8-bit register that specifies the SCI serial communication format and selects the
clock source for the baud rate generator.
The CPU can always read to SMR. The CPU should only perform write operations when making initial settings. Do not
use the CPU to perform writes during transmit, receive, or transmit/receive operation. SMR is initialized to H'00 by a
power-on reset and in hardware standby mode. The value is not retained in software standby mode and it is initialized after
release. It is not initialized by a manual reset.
• Bit 7—Communication Mode (C/A): Selects whether the SCI operates in asynchronous or synchronous mode.
Bit 7: C/A
0
1
Description
Asynchronous mode
Synchronous mode
(Initial value)
• Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data in asynchronous mode. In synchronous mode, the data
length is always eight bits, regardless of the CHR setting.
Bit 6: CHR
0
1
Description
Eight-bit data
(Initial value)
Seven-bit data
When 7-bit data is selected, the MSB (bit 7) of the transmit data register is not transmitted.
LSB-first/MSB-first selection is not available.
• Bit 5—Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the parity of receive data,
in asynchronous mode. In synchronous mode and when using a multiprocessor format, a parity bit is neither added nor
checked, regardless of the PE bit setting.
Bit 5: PE
0
1
Description
Parity bit not added or checked
(Initial value)
Parity bit added and checked
When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the
parity mode (O/E bit) setting. Receive data parity is checked according to the even/odd (O/E
bit) setting.
Rev.3.00 Mar. 12, 2008 Page 358 of 948
REJ09B0177-0300