SH7059 Datasheet, PDF (122/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. CPU
2.3.2 Addressing Modes
Table 2.8 describes addressing modes and effective address calculation.
Table 2.8 Addressing Modes and Effective Addresses
Addressing Mode
Direct register
addressing
Indirect register
addressing
Instruction
Format
Rn
@Rn
Effective Address Calculation
The effective address is register Rn. (The operand is the
contents of register Rn.)
The effective address is the contents of register Rn.
Equation
—
Rn
Rn
Rn
Post-increment indirect @Rn+
register addressing
Pre-decrement indirect @–Rn
register addressing
The effective address is the contents of register Rn.
A constant is added to the content of Rn after the
instruction is executed. 1 is added for a byte operation, 2
for a word operation, and 4 for a longword operation.
Rn
Rn
Rn + 1/2/4 ₊
1/2/4
Rn
(After the instruction
executes)
Byte: Rn + 1 → Rn
Word: Rn + 2 → Rn
Longword: Rn + 4 →
Rn
The effective address is the value obtained by subtracting Byte: Rn – 1 → Rn
a constant from Rn. 1 is subtracted for a byte operation, 2 _{Word: Rn – 2 → Rn}
for a word operation, and 4 for a longword operation.
Longword: Rn – 4 →
Rn
Rn (Instruction
Rn – 1/2/4 _–
Rn – 1/2/4
executed with Rn
after calculation)
Indirect register
addressing with
displacement
1/2/4
@(disp:4, Rn) The effective address is Rn plus a 4-bit displacement
(disp). The value of disp is zero-extended, and remains
the same for a byte operation, is doubled for a word
operation, and is quadrupled for a longword operation.
Rn
disp
(zero-extended)
+
×
Rn + disp × 1/2/4
Byte: Rn + disp
Word: Rn + disp × 2
Longword: Rn + disp
×4
Indirect indexed
register addressing
@(R0, Rn)
1/2/4
The effective address is the Rn value plus R0.
Rn
+
Rn + R0
R0
Rn + R0
Rev.3.00 Mar. 12, 2008 Page 32 of 948
REJ09B0177-0300