SH7059 Datasheet, PDF (137/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Table 2.18 Floating-Point Instructions
Instruction
FABS FRn
FADD FRm,FRn
FCMP/EQ FRm,FRn
FCMP/GT FRm,FRn
FDIV FRm,FRn
FLDI0 FRn
FLDI1 FRn
FLDS FRm,FPUL
FLOAT FPUL,FRn
FMAC FR0,FRm,FRn
FMOV FRm, FRn
FMOV.S @(R0,Rm),FRn
FMOV.S @Rm+,FRn
FMOV.S @Rm,FRn
FMOV.S FRm,@(R0,Rn)
FMOV.S FRm,@-Rn
FMOV.S FRm,@Rn
FMUL FRm,FRn
FNEG FRn
FSTS FPUL,FRn
FSUB FRm,FRn
FTRC FRm,FPUL
Instruction Code
1111nnnn01011101
1111nnnnmmmm0000
1111nnnnmmmm0100
1111nnnnmmmm0101
1111nnnnmmmm0011
1111nnnn10001101
1111nnnn10011101
1111mmmm00011101
1111nnnn00101101
1111nnnnmmmm1110
1111nnnnmmmm1100
1111nnnnmmmm0110
1111nnnnmmmm1001
1111nnnnmmmm1000
1111nnnnmmmm0111
1111nnnnmmmm1011
1111nnnnmmmm1010
1111nnnnmmmm0010
1111nnnn01001101
1111nnnn00001101
1111nnnnmmmm0001
1111mmmm00111101
Table 2.19 FPU-Related CPU Instructions
Instruction
LDS Rm,FPSCR
LDS Rm,FPUL
LDS.L @Rm+, FPSCR
LDS.L @Rm+, FPUL
STS FPSCR, Rn
STS FPUL,Rn
STS.L FPSCR,@-Rn
STS.L FPUL,@-Rn
Instruction Code
0100mmmm01101010
0100mmmm01011010
0100mmmm01100110
0100mmmm01010110
0000nnnn01101010
0000nnnn01011010
0100nnnn01100010
0100nnnn01010010
2. CPU
Operation
|FRn| → FRn
FRn + FRm → FRn
(FRn = FRm)? 1:0 → T
(FRn > FRm)? 1:0 → T
FRn/FRm → FRn
0x00000000 → FRn
0x3F800000 → FRn
FRm → FPUL
(float) FPUL → FRn
FR0 × FRm + FRn → FRn
FRm → FRn
(R0 + Rm) → FRn
(Rm) → FRn, Rm+ = 4
(Rm) → FRn
FRm → (R0 + Rn)
Rn– = 4, FRm → (Rn)
FRm → (Rn)
FRn × FRm → FRn
–FRn → FRn
FPUL → FRn
FRn – FRm → FRn
(long) FRm → FPUL
Execu-
tion
Cycles T Bit
1
—
1
—
1
Comparison result
1
Comparison result
13
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
Operation
Rm → FPSCR
Rm → FPUL
@Rm → FPSCR, Rm+ = 4
@Rm → FPUL, Rm+ = 4
FPSCR → Rn
FPUL → Rn
Rn– = 4, FPCSR → @Rn
Rn– = 4, FPUL → @Rn
Execu-
tion
Cycles T Bit
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
Rev.3.00 Mar. 12, 2008 Page 47 of 948
REJ09B0177-0300