SH7059 Datasheet, PDF (393/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
11.4.2 Status Flag Clearing
Clearing by CPU Program: The interrupt status flag is cleared when the CPU writes 0 to the flag after reading it while
set to 1.
The procedure and timing in this case are shown in figure 11.42.
Start
Read 1 from TSR
CK
Address
TSR write cycle
T1
T2
TSR address
Write 0 to TSR
Internal write
signal
Interrupt status flag
Interrupt status
flag cleared
IMF, ICF, CMF,
OVF, OSF, IIF
Interrupt request
signal
Figure 11.42 Procedure and Timing for Clearing by CPU Program
Clearing by DMAC: The interrupt status flag (ICF0A to ICF0D, CMF6A to CMF6D, CMF7A to CMF7D) is cleared
automatically during data transfer when the DMAC is activated by input capture or compare-match.
The procedure and timing in this case are shown in figure 11.43.
CK
Start
Clear request signal
from DMAC
Activate DMAC
Interrupt status
flag clear signal
Interrupt status flag
Interrupt status
ICF0B, CMF6
flag cleared during
data transfer
Interrupt request
signal
Figure 11.43 Procedure and Timing for Clearing by DMAC
Rev.3.00 Mar. 12, 2008 Page 303 of 948
REJ09B0177-0300