SH7059 Datasheet, PDF (378/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
11.3.6 Offset One-Shot Pulse Function and Output Cutoff Function
By making an appropriate setting in the timer connection register (TCNR), down-counting by channel 8 down-counters
(DCNT8A to DCNT8P) can be started using compare-match signals from channel 1 general registers (GR1A to GR1H) or
channel 1 and 2 compare-match registers (OCR1, OCR2A to OCR2H). DCNT8A to DCNT8H are connected to channel 1
OCR1 or GR1A to GR1H, and DCNT8I to DCNT8P are connected to channel 2 OCR2A to OCR2H or GR2A to GR2H.
This enables one-shot pulse output from the external pin (TO8A to TO8P) corresponding to DCNT. The down-count can
be forcibly stopped by making a setting in the one-shot pulse terminate register (OTR). On channel 1, down-count start or
termination by a GR or OCR compare-match can be selected with the trigger mode register (TRGMDR).
Making a setting in the timer start register (TSTR) starts an up-count by a free-running counter (TCNT) in channel 1 or 2.
When TCNT matches GR or OCR while connection is enabled by TCNR, the corresponding DSTR is automatically set
and DCNT starts counting down. At the same time, 1 is output from the corresponding external pin (TO8A to TO8P). By
making the appropriate setting in the interrupt enable register (TIER), an interrupt request can be sent to the CPU.
When TCNT1 matches GR or OCR, or TCNT2 matches GR, while channel 8 one-shot pulse termination by a channel 1 or
2 compare-match signal is enabled by OTR, the corresponding DSTR is automatically cleared and DCNT stops counting
down. DCNT is cleared to H'0000 at this time, and must be rewritten before the down-count is restarted.
DCNT8I to DCNT8P are connected to the reload register (RLDR8), and when the DSTR corresponding to DCNT8I to
DCNT8P is set, the DCNT8I to DCNT8P counter loads RLDR8 before starting the down-count.
An example of the offset one-shot pulse output function and output cutoff function is shown in figure 11.18.
Pφ
First prescaler 1
Second prescaler 1
Start trigger
(OSTRG1A-P)
Terminate trigger
(OSTRG0A-P)
Down-count
start trigger
(corresponding bit)
Down-counter
10A-10P clock
One-shot pulse
(TOA10-TOP10)
Down-counter
10A-10P
Synchronized with
down-counter clock
0009
0008
0007
0006
0005
0004 0003
0000
One-shot end
detection signal
One-shot end
interrupt (flag)
Figure 11.18 Offset One-Shot Pulse Output Function and Output Cutoff Function Operation
11.3.7 Interval Timer Operation
The interval interrupt request registers (ITVRR1, ITVRR2A, ITVRR2B) are connected to bits 6 to 9 and 10 to 13 of the
channel 0 free-running counter (TCNT0). The ITVRR registers are 8-bit registers; the upper 4 bits (ITVA) are used for
A/D converter activation, and the lower 4 bits (ITVE) are used for interrupt requests. ITVRR1 is connected to A/D
converter 2 (AD2), ITVRR2A to A/D converter 0 (AD0), and ITVRR2B to A/D converter 1 (AD1).
Rev.3.00 Mar. 12, 2008 Page 288 of 948
REJ09B0177-0300