SH7059 Datasheet, PDF (650/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. High-performance User Debug Interface (H-UDI)
The instruction code is 0011.
IDCODE: When the IDCODE instruction is enabled, the value of the ID code register is output from TDO with LSB first
when the TAP controller is in the Shift-DR state. While this instruction is being executed, the test circuit does not affect
the system circuit.
When the TAP controller is in the Test-Logic-Reset state, the instruction register is initialized to the IDCODE instruction.
The instruction code is 1110.
20.5.2 Notes on Use
1. Boundary scan mode does not cover clock-related signals (EXTAL, XTAL, CK, PLLCAP).
2. Boundary scan mode does not cover reset-related signals (RES, HSTBY).
3. Boundary scan mode does not cover H-UDI-related signals (TCK, TDI, TDO, TMS, TRST).
4. Boundary scan mode does not cover A/D-converter-related signals (AD0 to AN31).
5. While the HIGHZ instruction is being executed, the pull-up/pull-down settings of the AUD-related pins (AUDATA3
to ADUATA0, AUDCK, and AUDSYNC) are valid.
6. While the SAMPLE/PRELOAD instruction is being executed during the AUD reset (while AUDRST = low), the
latched input values of the AUDSYNC and AUDATA0 to AUDATA3 pins are fixed high.
7. While the SAMPLE/PRELOAD instruction is being executed during the reset state (while RES = low), the following
restrictions are put on I/O port pins.
The output values of PF6, PF7, PF9, and PF10 pins are fixed high in MCU extended mode. Other port F pins and the
port E and port H pins can latch input signals. The input values of other pins are fixed high.
8. While the EXTEST instruction is being executed during the reset state (while RES = low), the following restrictions
are put on I/O port pins.
PE0 to PE15, PF0 to PF7, PF9, and PF10 pins can be output. Port E, port F, and port H pins can be input.
However, the output values of PF6, PF7, PF9, and PF10 pins are fixed high in MCU extended mode.
The output settings for other pins are invalid, and their input values are fixed high.
9. While the CLAMP instruction is beign executed during the reset state (while RES = low), the following restrictions are
put on I/O port pins.
Only PE0 to PE15, PF0 to PF7, PF9, and PF10 pins can be output.
However, the output values of PF6, PF7, PF9, and PF10 pins are fixed high in MCU extended mode.
The output settings for other pins are invalid, and their input values are fixed high.
10. While the HIGHZ instruction is being executed during the reset state (while RES = low), the following restrictions are
put on I/O port pins. The output values of PF6, PF7, PF9, and PF10 pins are fixed high, and the HIGHZ instruction is
invalid.
Rev.3.00 Mar. 12, 2008 Page 560 of 948
REJ09B0177-0300