SH7059 Datasheet, PDF (165/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

6.7 Stack Status after Exception Processing Ends
The status of the stack after exception processing ends is as shown in table 6.11.
Table 6.11 Stack Status After Exception Processing Ends
Exception Type
Address error
Stack Status
SP
Address of instruction
after executed instruction
32 bits
SR
32 bits
6. Exception Processing
Trap instruction
SP
Address of instruction
after TRAPA instruction
32 bits
SR
32 bits
General illegal instruction
SP
Address of general
illegal instruction
SR
32 bits
32 bits
Interrupt
SP
Address of instruction
after executed instruction
32 bits
SR
32 bits
Illegal slot instruction
SP
Jump destination address
of delay branch instruction
32 bits
SR
32 bits
FPU exception
SP
Address of instruction after
FPU exception instruction
32
bits
SR
32 bits
6.8 Usage Notes
6.8.1 Value of Stack Pointer (SP)
The value of the stack pointer must always be a multiple of four. If it is not, an address error will occur when the stack is
accessed during exception processing.
6.8.2 Value of Vector Base Register (VBR)
The value of the vector base register must always be a multiple of four. If it is not, an address error will occur when the
stack is accessed during exception processing.
Rev.3.00 Mar. 12, 2008 Page 75 of 948
REJ09B0177-0300