SH7059 Datasheet, PDF (439/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14.3 Operation
14. Compare Match Timer (CMT)
14.3.1 Cyclic Count Operation
When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR bit of CMSTR is set to
1, CMCNT begins incrementing with the selected clock. When the CMCNT counter value matches that of the compare
match constant register (CMCOR), the CMCNT counter is cleared to H'0000 and the CMF flag of the CMCSR register is
set to 1. If the CMIE bit of the CMCSR register is set to 1 at this time, a compare match interrupt (CMI) is requested. The
CMCNT counter begins counting up again from H'0000.
Figure 14.2 shows the compare match counter operation.
CMCNT value
CMCOR
Counter cleared by
CMCOR compare match
H'0000
Figure 14.2 Counter Operation
Time
14.3.2 CMCNT Count Timing
One of four clocks (Pφ/8, Pφ/32, Pφ/128, Pφ/512) obtained by dividing the peripheral clock (Pφ) can be selected by the
CKS1 and CKS0 bits of CMCSR. Figure 14.3 shows the timing.
Pφ
Internal clock
CMCNT input
clock
CMCNT
N–1
14.4 Interrupts
N
Figure 14.3 Count Timing
N+1
14.4.1 Interrupt Sources and DTC Activation
The CMT has a compare match interrupt for each channel, with independent vector addresses allocated to each of them.
The corresponding interrupt request is output when interrupt request flag CMF is set to 1 and interrupt enable bit CMIE
has also been set to 1.
When activating CPU interrupts by interrupt request, the priority between the channels can be changed by means of
interrupt controller settings. See section 7, Interrupt Controller (INTC), for details.
Rev.3.00 Mar. 12, 2008 Page 349 of 948
REJ09B0177-0300