SH7059 Datasheet, PDF (239/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Figure 10.9 shows an example of DMA transfer timing in burst mode.
10. Direct Memory Access Controller (DMAC)
Bus cycle
CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU
Read/Write Read/Write Read/Write
Figure 10.9 DMA Transfer Timing Example in Burst Mode
10.3.7 Relationship between Request Modes and Bus Modes by DMA Transfer Category
Table 10.4 shows the relationship between request modes and bus modes by DMA transfer category.
Table 10.4 Relationship between Request Modes and Bus Modes by DMA Transfer Category
Address
Mode Transfer Category
Request Bus Transfer Usable
Mode
Mode Size (Bits) Channels
Dual
External memory and external memory
Any*¹
B/C 8/16/32 0–3
External memory and memory-mapped external device
Any*¹
B/C 8/16/32 0–3
Memory-mapped external device and memory-mapped external Any*¹
device
B/C 8/16/32 0–3
External memory and on-chip memory
Any*¹
B/C 8/16/32 0–3
External memory and on-chip peripheral module
Any*²
B/C*³ 8/16/32*⁴ 0–3
Memory-mapped external device and on-chip memory
Any*¹
B/C 8/16/32 0–3
Memory-mapped external device and on-chip peripheral module Any*²
B/C*³ 8/16/32*⁴ 0–3
On-chip memory and on-chip memory
Any*¹
B/C 8/16/32 0–3
On-chip memory and on-chip peripheral module
Any*²
B/C*³ 8/16/32*⁴ 0–3
On-chip peripheral module and on-chip peripheral module
Any*²
B/C*³ 8/16/32*⁴ 0–3
Legend:
B: Burst
C: Cycle-steal
Notes: 1. Auto-request or on-chip peripheral module request enabled. However, in the case of an on-chip peripheral
module request, it is not possible to specify the SCI, HCAN0, SSU*⁵, or A/D converter for the transfer request
source.
2. Auto-request or on-chip peripheral module request possible. However, if the transfer request source is also the
SCI, HCAN0, SSU*⁵, or A/D converter, the transfer source or transfer destination must be same as the transfer
source.
3. When the transfer request source is the SCI, or SSU*⁵, only cycle-steal mode is possible.
4. Access size permitted by the on-chip peripheral module register that is the transfer source or transfer
destination.
5. SSU: Synchronous Serial Communication Unit
10.3.8 Bus Mode and Channel Priorities
If, for example, a transfer request is issued for channel 0 while transfer is in progress on lower-priority channel 1 in burst
mode, transfer is started immediately on channel 0.
In this case, if channel 0 is set to burst mode, channel 1 transfer is continued after completion of all transfers on channel 0.
If channel 0 is set to cycle-steal mode, channel 1 transfer is continued only if a channel 0 transfer request has not been
issued; if a transfer request is issued, channel 0 transfer is started immediately.
Rev.3.00 Mar. 12, 2008 Page 149 of 948
REJ09B0177-0300