SH7059 Datasheet, PDF (623/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Multi-Trigger A/D Converter (MTAD)
19.3.5 Interrupts
Each of channels 0 and 1 generate interrupts from seven sources, that is, a total of 14 sources listed below.
Module
ADT0
IPR Bit
IPRJ
(11 to 8)
Vector
ADI0
Vector
Number
189
Conditions of Interrupt Generation
Multi-trigger A/D conversion ends when the interrupt is enabled by
TADE0A
Multi-trigger A/D conversion ends when the interrupt is enabled by
TADE0B
ADCNT0 matches ADCYLR0 when the interrupt is enabled by CYE0
ADCNT0 matches ADDR0A when the interrupt is enabled by ADDE0A
ADCNT0 matches ADDR0B when the interrupt is enabled by ADDE0B
ADCNT0 matches ADGR0A when the interrupt is enabled by
ADCME0A
ADCNT0 matches ADGR0B when the interrupt is enabled by
ADCME0B
Module
ADT1
IPR Bit
IPRJ
(7 to 4)
Vector
ADI1
Vector
Number
193
Conditions of Interrupt Generation
Multi-trigger A/D conversion ends when the interrupt is enabled by
TADE1A
Multi-trigger A/D conversion ends when the interrupt is enabled by
TADE1B
ADCNT1 matches ADCYLR1 when the interrupt is enabled by CYE1
ADCNT1 matches ADDR1A when the interrupt is enabled by ADDE1A
ADCNT1 matches ADDR1B when the interrupt is enabled by ADDE1B
ADCNT1 matches ADGR1A when the interrupt is enabled by
ADCME1A
ADCNT1 matches ADGR1B when the interrupt is enabled by
ADCME1B
19.3.6 Usage Notes
1. When a conflict occurs between a write to ADCNT and clearing of the counter by a compare match
When a compare match occurs during T2 state of a CPU cycle for writing to ADCNT, ADCNT is not cleared but is
written to.
However, a compare match remains effective, thus allowing a write of 1 to the interrupt status flag and external
waveform output, similar to regular compare matches.
2. When a conflict occurs between a write to ADCNT and incrementing of the counter The counter is not incremented but
is written to.
3. When a conflict occurs between clearing of the interrupt status flag and setting of the flag by interrupt generation
When any event, such as a compare match and overflow, occurs during T2 state of a CPU cycle for writing 0 to the
interrupt status flag, the compare match takes priority thus allowing the interrupt status flag to be set.
4. When reading the continuous scan A/D conversion data during the multi-trigger A/D conversion is performed
Reading is performed by the DMA. Following errors are generated according to the interrupt timing.
When reading ADDR of the first channel by the continuous scan interrupt, if MTAD is executed on the last channel in
the previous scan, the data may be overwritten again in this scan because the first channel is converted.
Rev.3.00 Mar. 12, 2008 Page 533 of 948
REJ09B0177-0300