SH7059 Datasheet, PDF (65/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Differences between SH7058 and SH7058S/SH7059
SH7058 (Rev.3, REJ09B0046-0300H)
SH7058S/SH7059
25.4.1 Transition to Software Standby Mode
950
… The SH7058 switches from the program execution state
to software standby mode. In software standby mode,
power consumption is greatly reduced by halting not only
the CPU, but the clock and on-chip peripheral modules as
well. CPU register contents and on-chip RAM data are held
as long as the prescribed voltages are applied (when the
RAME bit in SYSCR1 is 0). The register contents of some
on-chip peripheral modules are initialized, but some are
not. The I/O port state can be selected as held or high
impedance by the port high impedance bit (HIZ) in SBYCR.
27.4.1 Transition to Software Standby Mode
Description amended
… This LSI switches from the program execution state to
software standby mode. In software standby mode, power
consumption is drastically reduced by halting all the
functions in this LSI and stopping the internal power supply
except the on-chip RAM. The contents of the on-chip RAM
are held as long as the given voltages are suppled. For
details on the regiseter states of on-chip peripheral
modules, see Appendix A.2, Register States in Reset and
Power-Down States. For details on the pin states, see
Appendix B, Pin States.
25.4.2 Canceling Software Standby Mode
950
Software standby mode is canceled by an NMI interrupt or
a power-on reset.
27.4.2 Canceling Software Standby Mode
Description amended
Software standby mode is canceled by a rising edge of the
NMI pin or a power-on reset.
Cancellation by NMI:
Cancellation by Power-On Reset:
951
A power-on reset of the SH7058 caused by driving the
RES pin low cancels software standby mode.
25.4.3 Software Standby Mode Application Example
952
This example describes a transition to software standby
mode on the falling edge of the NMI signal, and
cancellation on the rising edge of the NMI signal. The
timing is shown in figure 25.3.
Cancellation by a rising edge of the NMI pin:
Replaced
Cancellation by Power-On Reset:
Description added
When the RES pin is driven low, this LSI enters the
power-on reset state and software standby mode is
canceled. At this time, the software standby flag (SSBYF)
is cleared to 0.
27.4.3 Software Standby Mode Application Example
Description amended
In this example, the NMI exception processing is started by
the falling edge of the NMI signal: a transition to software
standby mode is made; the mode is canceled by the rising
edge of the NMI signal. The timing is shown in figure 27.3
When the NMI pin is changed from high to low level while
the NMI edge select bit (NMIE) in ICR is set to 0 (falling
edge detection), the NMI interrupt is accepted. When the
NMIE bit is set to 1 (rising edge detection) by the NMI
exception service routine, the software standby bit (SSBY)
in SBYCR is set to 1, and a SLEEP instruction is executed,
software standby mode is entered.
When the NMI signal is driven from high to low while the
NMI edge select bit (NMIE) in ICR is set to 0 (falling edge
detection), the NMI interrupt is accepted. When the NMIE
bit is set to 1 (rising edge detection) by the NMI exception
service routine and the SLEEP instruction is executed with
the software standby bit (SSBY) in SBYCR set to 1,
software standby mode is entered and the internal power
supply is stopped.
Thereafter, software standby mode is canceled when the
NMI pin is changed from low to high level.
Thereafter, software standby mode is canceled when the
NMI signal is driven from low to high. After the internal
power supply is provided, the clock starts oscillation, and
the oscillation settling counter overflows, the power-on
reset exception processing begins.
Figure 25.3 Software Standby Mode NMI Timing
(Application Example)
Figure 27.3 Software Standby Mode NMI Timing
(Application Example)
Figure replaced
Rev.3.00 Mar. 12, 2008 Page lxv of xc
REJ09B0177-0300