SH7059 Datasheet, PDF (482/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Serial Communication Interface (SCI)
Figure 15.22 shows an example of the SCI receive operation.
Transfer direction
Serial clock
Serial
data
RDRF
Bit 7 Bit 0
Bit 7 Bit 0 Bit 1
Bit 6 Bit 7
ORER
RXI interrupt
request
Read data with RXI
interrupt processing
routine and clear
RDRF bit to 0
1 frame
RXI interrupt
request
ERI interrupt
request generated
by overrun error
Figure 15.22 Example of SCI Receive Operation
In receiving, the SCI operates as follows:
1. The SCI synchronizes with serial clock input or output and initializes internally.
2. Receive data is shifted into RSR in order from the LSB to the MSB. After receiving the data, the SCI checks that
RDRF is 0 so that receive data can be loaded from RSR into RDR. If this check passes, the SCI sets RDRF to 1 and
stores the receive data in RDR. If the check does not pass (receive error), the SCI operates as indicated in table 15.11
and no further transmission or reception is possible. If the error flag is set to 1, the RDRF bit is not set to 1 during
reception, even if the RDRF bit is 0 cleared. When restarting reception, be sure to clear the error flag.
3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCR, the SCI requests a
receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the receive-data-full interrupt enable bit (RIE) in SCR
is also set to 1, the SCI requests a receive-error interrupt (ERI).
Rev.3.00 Mar. 12, 2008 Page 392 of 948
REJ09B0177-0300