SH7059 Datasheet, PDF (832/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

25. ROM (SH7059)
(2.1) Flash programming/erasing frequency parameter (FPEFEQ: general register R4 of CPU)
This parameter sets the operating frequency of the CPU.
For the range of the operating frequency of this LSI, see section 29.3.2, Clock Timing.
Bit :
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
Bit :
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
Bit :
15
14
13
12
11
10
9
8
F15
F14
F13
F12
F11
F10
F9
F8
Bit :
7
6
5
4
3
2
1
0
F7
F6
F5
F4
F3
F2
F1
F0
• Bits 31 to 16—Unused: Return 0.
• Bits 15 to 0—Frequency Set (F15 to F0): Set the operating frequency of the CPU. The setting value must be calculated
as the following methods.
1. The operating frequency which is shown in MHz units must be rounded in a number to three decimal places and be
shown in a number of two decimal places.
2. The centuplicated value is converted to the binary digit and is written to the FPEFEQ parameter (general register R4).
For example, when the operating frequency of the CPU is 28.882 MHz, the value is as follows.
1. The number to three decimal places of 28.882 is rounded and the value is thus 28.88.
2. The formula that 28.88 × 100 = 2888 is converted to the binary digit and b'0000, 1011, 0100, 1000 (H'0B48) is set
to R4.
(2.2) Flash user branch address setting parameter (FUBRA: general register R5 of CPU)
This parameter sets the user branch destination address. The user program which has been set can be executed in
specified processing units when programming and erasing.
Bit :
31
30
29
28
27
26
25
24
UA31 UA30 UA29 UA28 UA27 UA26 UA25 UA24
Bit :
23
22
21
20
19
18
17
16
UA23 UA22 UA21 UA20 UA19 UA18 UA17 UA16
Bit :
15
14
13
12
11
10
9
8
UA15 UA14 UA13 UA12 UA11 UA10 UA9 UA8
Bit :
7
6
5
4
3
2
1
0
UA7 UA6 UA5 UA4 UA3 UA2 UA1 UA0
• Bits 31 to 0—User Branch Destination Address (UA31 to UA0): When the user branch is not required, address 0
(H'00000000) must be set.
The user branch destination must be an area other than the flash memory, an area other than the RAM area in which on-
chip program has been transferred, or the external bus space.
Note that the CPU must not branch to an area without the execution code and get out of control. The on-chip program
download area and stack area must not be overwritten. If CPU runaway occurs or the download area or stack area is
overwritten, the value of flash memory cannot be guaranteed.
Rev.3.00 Mar. 12, 2008 Page 742 of 948
REJ09B0177-0300