SH7059 Datasheet, PDF (485/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Serial Communication Interface (SCI)
15.5.3 Break Detection and Processing (Asynchoronous Mode Only)
Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state,
the input from the RxD pin consists of all 0s, so FER is set and the parity error flag (PER) may also be set. In the break
state, the SCI receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again.
15.5.4 Sending a Break Signal (Asynchoronous Mode Only)
The TxD pin becomes a general I/O pin with the I/O direction and level determined by the I/O port data register (DR) and
pin function controller (PFC) control register (CR). These conditions allow break signals to be sent. The DR value is
substituted for the marking status until the PFC is set. Consequently, the output port is set to initially output a 1. To send a
break in serial transmission, first clear the DR to 0, then establish the TxD pin as an output port using the PFC. When TE
is cleared to 0, the transmission section is initialized regardless of the present transmission status.
15.5.5 Receive Error Flags and Transmitter Operation (Synchronous Mode Only)
When a receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting even if TDRE is set to 1. Be
sure to clear the receive error flags to 0 before starting to transmit. Note that clearing RE to 0 does not clear the receive
error flags.
15.5.6 Receive Data Sampling Timing and Receive Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times the transfer rate. In receiving, the
SCI synchronizes internally with the falling edge of the start bit, which it samples on the base clock. Receive data is
latched on the rising edge of the eighth base clock pulse (figure 15.24).
16 clocks
8 clocks
0
78
15 0
78
Base clock
–7.5 clocks +7.5 clocks
Receive
data (RxD)
Start bit
D0
15 0
5
D1
Synchronization
sampling timing
Data
sampling timing
Figure 15.24 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be expressed as:
M = 0.5 – ¹ – (L – 0.5) F – ^{D – 0.5} (1 + F) × 100%
2N
N
M : Receive margin (%)
N : Ratio of clock frequency to bit rate (N = 16)
D : Clock duty cycle (D = 0 − 1.0)
L : Frame length (L = 9 − 12)
F : Absolute deviation of clock frequency
Rev.3.00 Mar. 12, 2008 Page 395 of 948
REJ09B0177-0300