SH7059 Datasheet, PDF (181/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Interrupt Controller (INTC)
• Bits 7 to 0—IRQ0–IRQ7 Flags (IRQ0F–IRQ7F): These bits display the IRQ0–IRQ7 interrupt request status.
Bits 7-0: IRQ0F–IRQ7F
0
Detection Setting
Level detection
Edge detection
1
Note: n = 7 to 0
Level detection
Edge detection
Description
No IRQn interrupt request exists
[Clearing condition]
When IRQn input is high
No IRQn interrupt request was detected
(Initial value)
[Clearing conditions]
• When 0 is written after reading IRQnF = 1
• When IRQn interrupt exception processing has been executed
An IRQn interrupt request exists
Setting condition: When IRQn input is low
An IRQn interrupt request was detected
Setting condition: When a falling edge occurs at an IRQn input
7.4 Interrupt Operation
7.4.1 Interrupt Sequence
The sequence of interrupt operations is explained below. Figure 7.2 is a flowchart of the operations.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest priority interrupt in the interrupt requests sent, following the priority levels
set in interrupt priority registers A–L (IPRA–IPRL). Lower-priority interrupts are ignored. They are held pending until
interrupt requests designated as edge-detect type are accepted. For IRQ interrupts, however, withdrawal is possible by
accessing the IRQ status register (ISR). See section 7.2.4, IRQ Interrupts, for details. Interrupts held pending due to
edge detection are cleared by a power-on reset or a manual reset. If two of these interrupts have the same priority level
or if multiple interrupts occur within a single module, the interrupt with the highest default priority or the highest
priority within its IPR setting range (as indicated in table 7.3) is selected.
3. The interrupt controller compares the priority level of the selected interrupt request with the interrupt mask bits (I3–I0)
in the CPU’s status register (SR). If the request priority level is equal to or less than the level set in I3–I0, the request is
ignored. If the request priority level is higher than the level in bits I3–I0, the interrupt controller accepts the interrupt
and sends an interrupt request signal to the CPU.
4. When the interrupt controller accepts an interrupt, a low level is output from the IRQOUT pin.
5. The CPU detects the interrupt request sent from the interrupt controller when it decodes the next instruction to be
executed. Instead of executing the decoded instruction, the CPU starts interrupt exception processing (figure 7.4).
6. SR and PC are saved onto the stack.
7. The priority level of the accepted interrupt is copied to the interrupt mask level bits (I3 to I0) in the status register (SR).
8. When the accepted interrupt is sensed by level or is from an on-chip peripheral module, a high level is output from the
IRQOUT pin. When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the point
when the CPU starts interrupt exception processing instead of instruction execution as noted in 5 above. However, if
the interrupt controller accepts an interrupt with a higher priority than one it is in the process of accepting, the
IRQOUT pin will remain low.
9. The CPU reads the start address of the exception service routine from the exception vector table for the accepted
interrupt, jumps to that address, and starts executing the program there. This jump is not a delay branch.
Rev.3.00 Mar. 12, 2008 Page 91 of 948
REJ09B0177-0300