SH7059 Datasheet, PDF (297/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

TSR1B: TSR1B indicates the status of channel 1 compare-match and overflow.
Bit:
15
14
13
12
11
—
—
—
—
—
Initial value:
0
0
0
0
0
R/W:
R
R
R
R
R
11. Advanced Timer Unit-II (ATU-II)
10
9
8
—
—
OVF1B
0
0
0
R
R
R/(W)*
Bit:
7
6
5
4
3
2
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
Note: * Only 0 can be written, to clear the flag.
• Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 8—Overflow Flag 1B (OVF1B): Status flag that indicates TCNT1B overflow.
Bit 8: OVF1B
0
1
Description
[Clearing condition]
When OVF1B is read while set to 1, then 0 is written to OVF1B
[Setting condition]
When the TCNT1B value overflows (from H'FFFF to H'0000)
1
0
—
CMF1
0
0
R
R/(W)*
(Initial value)
• Bits 7 to 1—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 0—Compare-Match Flag 1 (CMF1): Status flag that indicates OCR1 compare-match.
Bit 0: CMF1
0
1
Description
[Clearing condition]
When CMF1 is read while set to 1, then 0 is written to CMF1
[Setting condition]
When TCNT1B = OCR1
(Initial value)
Timer Status Registers 2A and 2B (TSR2A, TSR2B)
TSR2A: TSR2A indicates the status of channel 2 input capture, compare-match, and overflow.
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
OVF2A
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/(W)*
Bit:
Initial value:
R/W:
7
IMF2H
0
R/(W)*
6
IMF2G
0
R/(W)*
5
IMF2F
0
R/(W)*
Note: * Only 0 can be written to clear the flag.
4
IMF2E
0
R/(W)*
3
IMF2D
0
R/(W)*
2
IMF2C
0
R/(W)*
1
IMF2B
0
R/(W)*
0
IMF2A
0
R/(W)*
• Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0.
Rev.3.00 Mar. 12, 2008 Page 207 of 948
REJ09B0177-0300