SH7059 Datasheet, PDF (594/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

18. A/D Converter
Bit:CH2
0
1
Bit:CH1
0
1
0
1
Bit:CH0
0
1
0
1
0
1
0
1
Single Mode
AN24 (Initial value)
AN25
AN26
AN27
AN28
AN29
AN30
AN31
Analog Input Channels
4-Channel Scan Mode 8-Channel Scan Mode
AN24
AN24, AN28
AN24, AN25
AN24, AN25, AN28, AN29
AN24–AN26
AN24–AN26, AN28–AN30
AN24–AN27
AN24–AN31
AN28
AN24, AN28
AN28, AN29
AN24, AN25, AN28, AN29
AN28–AN30
AN24–AN26, AN28–AN30
AN28–AN31
AN24–AN31
18.2.5 A/D Trigger Registers 0 to 2 (ADTRGR0 to ADTRGR2)
The A/D trigger registers (ADTRGR0 to ADTRGR2) are 8-bit readable/writable registers that select the A/D0, A/D1, and
A/D2 triggers. Either external pin (ADTRG0, ADTRG1) or ATU-II (ATU-II interval timer A/D conversion request)
triggering can be selected.
ADTRGR0 to ADTRGR2 are initialized to H'FF by a power-on reset, in hardware standby mode and software standby
mode.
Bit:
7
6
5
4
3
2
1
0
EXTRG
—
—
—
—
—
—
—
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R
R
R
R
R
R
R
• Bit 7—Trigger Enable (EXTRG): Selects external pin input (ADTRG0, ADTRG1) or the ATU-II interval timer A/D
conversion request.
Bit 7:EXTRG
0
1
Description
A/D conversion is triggered by the ATU-II channel 0 interval timer A/D conversion request
A/D conversion is triggered by external pin input (ADTRG)
(Initial value)
In order to select external triggering or ATU-II triggering, the TGRE bit in ADCR0 to ADCR2 must be set to 1. For
details, see section 18.2.3, A/D Control Registers 0 to 2 (ADCR0 to ADCR2).
• Bits 6 to 0—Reserved: These bits are always read as 1. The write value should always be 1.
Rev.3.00 Mar. 12, 2008 Page 504 of 948
REJ09B0177-0300