SH7059 Datasheet, PDF (240/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Direct Memory Access Controller (DMAC)
10.3.9 Source Address Reload Function
Channel 2 has a source address reload function. This returns to the first value set in the source address register (SAR2)
every four transfers by setting the RO bit of CHCR2 to 1. Figure 10.10 illustrates this operation. Figure 10.11 is a timing
chart for use of channel 2 only with the following transfer conditions set: burst mode, auto-request, 16-bit transfer data
size, SAR2 incremented, DAR2 fixed, reload function on.
DMAC
DMAC control block
Transfer
request
Reload control
4th count
RO bit = 1
CHCR2
Count signal
DMATCR2
Reload signal
Reload
signal
SAR2
(initial value)
SAR2
Figure 10.10 Source Address Reload Function
CK
Internal
address bus
Internal
data bus
SAR2 DAR2 SAR2+2 DAR2 SAR2+4 DAR2 SAR2+6 DAR2
SAR2 data
SAR2+2 data
SAR2+4 data
SAR2+6 data
SAR2 DAR2
SAR2 data
1st channel 2
transfer
SAR2 output
DAR2 output
2nd channel 2
transfer
3rd channel 2
transfer
4th channel 2
transfer
SAR2+2 output
DAR2 output
SAR2+4 output
DAR2 output
SAR2+6 output
DAR2 output
5th channel 2
transfer
SAR2 output
DAR2 output
After SAR2+6 output, SAR2 is reloaded
Bus right is returned one time in four
Figure 10.11 Source Address Reload Function Timing Chart
The reload function can be executed whether the transfer data size is 8, 16, or 32 bits.
DMATCR2, which specifies the number of transfers, is decremented by 1 at the end of every single-transfer-unit transfer,
regardless of whether the reload function is on or off. Therefore, when using the reload function in the on state, a multiple
of 4 must be specified in DMATCR2. Operation will not be guaranteed if any other value is set. Also, the counter which
counts the occurrence of four transfers for address reloading is reset by clearing of the DME bit in DMAOR or the DE bit
in CHCR2, setting of the transfer end flag (the TE bit in CHCR2), NMI input, and setting of the AE flag (address error
generation in DMAC transfer), as well as by a reset and in software standby mode, but SAR2, DAR2, DMATCR2, and
other registers are not reset. Consequently, when one of these sources occurs, there is a mixture of initialized counters and
Rev.3.00 Mar. 12, 2008 Page 150 of 948
REJ09B0177-0300