SH7059 Datasheet, PDF (647/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. High-performance User Debug Interface (H-UDI)
Figures 20.3, 20.4, and 20.5 show the timing of data transfer between an external device and the H-UDI.
Serial data
Instruction _{SDTRF Input}
Input/
output
1
0
1
H-UDI interrupt
request
SDTRF
(in SDSR)^*1
SDSR and
SDDR MUX^*2
Shift
enabled
SDDR access
state
Shift
disabled
Shift
enabled
SDSR SDDR
SDSR
SDDR
Shift
CPU
Shift
CPU
SDSR serial transfer
(monitoring)
Notes: 1. SDTRF flag (in SDSR): Indicates whether SDDR access by the CPU or serial transfer
data input/output to SDDR is possible.
1 SDDR is shift-disabled. SDDR access by the CPU is enabled.
2 SDDR is shift-enabled. Do not access SDDR until SDTRF = 0.
Conditions:
• SDTRF = 1
— When TRST = 0
— When the CPU writes 1
— In BYPASS mode
• SDTRF = 0
— End of SDDR shift access in serial transfer
2. SDSR/SDDR (Update-DR state) internal MUX switchover timing
• Switchover from SDSR to SDDR: On completion of serial transfer in which
SDTRF = 1 is output from TDO
• Switchover from SDDR to SDSR: On completion of serial transfer to SDDR
Figure 20.3 Data Input/Output Timing Chart (1)
Rev.3.00 Mar. 12, 2008 Page 557 of 948
REJ09B0177-0300