SH7059 Datasheet, PDF (529/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
Bit
Bit Name Initial Value R/W Description
4
MCR4
0
R/W CAN Endian Mode
Controls whether the HCAN should transmit the messages in little endian
mode or big endian mode. By using this bit, in other words, it is possible to
set different endian mode to the HCAN and the external network. Note that
this bit is only valid when data field is transmitted/received.
0: Data field transmitted/received in big endian mode
1: Data field transmitted/received in little endian mode
3
—
0
R/W Reserved
The initial value should be retained.
2
MCR2
0
R/W Message Transmission Priority
Selects the order of transmission for pending transmit data.
When this bit is set, pending transmit data are sent in order of the bit position
in the transmit wait register (TXPR). The order of transmission starts from
mailbox 31 as the highest priority, and then down to mailbox 1 (if those
mailboxes are configured for transmission).
Important: This function cannot be used for timer triggered transmission.
When this bit is cleared, all messages for transmission are queued with
respect to their priority (by running internal arbitration). The highest priority
message has the arbitration field with the lowest digital value and is
transmitted first. The internal arbitration includes the RTR bit and the IDE bit.
0: Transmission order determined by message ID priority
1: Transmission order determined by mailbox number priority (mailbox 31 →
mailbox 1)
1
MCR1
0
R/W Halt Request
Setting this bit causes the CAN controller to complete its current operation
and then to cut off the CAN bus. The HCAN remains in halt mode until this
bit is cleared. During halt mode, the CAN interface does not join the CAN
bus activity or does not store messages nor transmit messages. All of the
registers and mailbox contents are retained. The HCAN will complete the
current operation if it is a transmitter or a receiver, and then enter halt mode.
If the CAN bus is in the idle or intermission state, the HCAN will enter halt
mode immediately. Entering halt mode is notified by IRR0 and GSR4. If a
halt request is made during bus off, the HCAN-II remains bus off even after
128 × 11 recessive bits. In order to exit this state, the halt state needs to be
canceled by software.
In halt mode, the HCAN configuration can be modified as it does not join the
bus activity. This bit has to be cleared to 0 to re-join the CAN bus. After this
bit is cleared, the CAN interface waits until it detects 11 recessive bits, and
then joins the CAN bus.
0: Normal operating mode
1: Halt mode transition request
Rev.3.00 Mar. 12, 2008 Page 439 of 948
REJ09B0177-0300