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SH7059 Datasheet, PDF (488/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer
16. Synchronous Serial Communication Unit (SSU)
Figure 16.1 shows a block diagram of the SSU.
Module data bus
SSTDR 0
SSTDR 1
SSTDR 2
SSTDR 3
SSRDR 0
SSRDR 1
SSRDR 2
SSRDR 3
SSCRH
SSCRL
SSMR
SSER
SSSR
Control circuit
Internal data bus
OEI
CEI
RXI
TXI
TEI
SSTRSR
Selector
Clock
Clock
selector
φ
φ/4
φ/8
φ/16
φ/32
φ/64
φ/128
φ/256
SSI
SSO
SCS
SSCK (External clock)
Legend:
SSCRH:
SS control register H
SSCRL:
SS control register L
SSMR:
SS mode register
SSER:
SS enable register
SSSR:
SS status register
SSTDR0 to SSTDR3: SS transmit data register 0 to 3
SSRDR0 to SSRDR3: SS receive data register 0 to 3
SSTRSR:
SS transmit/recive shift register
Figure 16.1 Block Diagram of SSU
Rev.3.00 Mar. 12, 2008 Page 398 of 948
REJ09B0177-0300