SH7059 Datasheet, PDF (178/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Interrupt Controller (INTC)
Interrupt Source
HCAN0
WDT
HCAN1
ERS0
OVR0
RM0
SLE0
ITI
ERS1
OVR1
RM1
SLE1
Interrupt Vector
Vector
No.
Vector Table
Address
Offset
220
H'00000370 to
H'00000373
221
H'00000374 to
H'00000377
222
H'00000378 to
H'0000037B
223
H'0000037C to
H'0000037F
224
H'00000380 to
H'00000383
228
H'00000390 to
H'00000393
229
H'00000394 to
H'00000397
230
H'00000398 to
H'0000039B
231
H'0000039C to
H'0000039F
Interrupt
Priority
(Initial
Value)
0 to 15 (0)
0 to 15 (0)
0 to 15 (0)
Corre-
sponding
IPR (Bits)
IPRL (11–8)
IPRL (7–4)
IPRL (3–0)
Priority
within IPR
Default
Setting Range Priority
↑
1
High
2
3
↓
4
↑
1
2
3
↓
4
Low
7.3 Description of Registers
7.3.1 Interrupt Priority Registers A–L (IPRA–IPRL)
Bit:
15
14
13
12
11
10
9
8
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Interrupt priority registers A–L (IPRA–IPRL) are 16-bit readable/writable registers that set priority levels from 0 to 15 for
IRQ interrupts and on-chip peripheral module interrupts. Correspondence between interrupt request sources and each of
the IPRA–IPRL bits is shown in table 7.4.
Rev.3.00 Mar. 12, 2008 Page 88 of 948
REJ09B0177-0300