SH7059 Datasheet, PDF (189/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8.2 Register Descriptions
8. User Break Controller (UBC)
8.2.1 User Break Address Register (UBAR)
UBARH:
Bit:
Initial value:
R/W:
15
UBA31
0
R/W
14
UBA30
0
R/W
13
UBA29
0
R/W
12
UBA28
0
R/W
11
UBA27
0
R/W
10
UBA26
0
R/W
9
UBA25
0
R/W
8
UBA24
0
R/W
Bit:
Initial value:
R/W:
7
UBA23
0
R/W
6
UBA22
0
R/W
5
UBA21
0
R/W
4
UBA20
0
R/W
3
UBA19
0
R/W
2
UBA18
0
R/W
1
UBA17
0
R/W
0
UBA16
0
R/W
UBARL:
Bit:
Initial value:
R/W:
15
UBA15
0
R/W
14
UBA14
0
R/W
13
UBA13
0
R/W
12
UBA12
0
R/W
11
UBA11
0
R/W
10
UBA10
0
R/W
9
UBA9
0
R/W
8
UBA8
0
R/W
Bit:
Initial value:
R/W:
7
UBA7
0
R/W
6
UBA6
0
R/W
5
UBA5
0
R/W
4
UBA4
0
R/W
3
UBA3
0
R/W
2
UBA2
0
R/W
1
UBA1
0
R/W
0
UBA0
0
R/W
The user break address register (UBAR) consists of user break address register H (UBARH) and user break address
register L (UBARL). Both are 16-bit readable/writable registers. UBARH stores the upper bits (bits 31 to 16) of the
address of the break condition, while UBARL stores the lower bits (bits 15 to 0). UBARH and UBARL are initialized to
H'0000 by a power-on reset, in module standby mode, and in software standby mode.
• UBARH Bits 15 to 0—User Break Address 31 to 16 (UBA31 to UBA16): These bits store the upper bit values (bits 31
to 16) of the address of the break condition.
• UBARL Bits 15 to 0—User Break Address 15 to 0 (UBA15 to UBA0): These bits store the lower bit values (bits 15 to
0) of the address of the break condition.
Rev.3.00 Mar. 12, 2008 Page 99 of 948
REJ09B0177-0300