SH7059 Datasheet, PDF (261/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
Block Diagram of Channel 0: Figure 11.2 shows a block diagram of ATU-II channel 0.
STR0
Prescaler 1
TI0A
TI0B
TI0C
TI0D
ICR0AH
ICR0BH
ICR0CH
ICR0DH
TCNT0H
ICR0AL
ICR0BL
ICR0CL
ICR0DL
TCNT0L
TIOR0
TIER0
ITVRR1
ITVRR2A
ITVRR2B
TSR0
I/O control
Control
logic
TRGOD
(OCR10B
compare-match signal)
A/D converter
trigger
Overflow interrupt
signal
Interval interrupt
Internal data bus and address bus
OSBR (ch1, ch2)
Figure 11.2 Block Diagram of Channel 0
Rev.3.00 Mar. 12, 2008 Page 171 of 948
REJ09B0177-0300