SH7059 Datasheet, PDF (382/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
started. If PWM operation is performed after setting H'FFFF in the cycle register, the cycle register's compare-match flag
and overflow flag will be set simultaneously.
Note that 0% or 100% duty output is not possible in channel 3 to 5 PWM mode.
An example of channel 3 to 5 PWM mode operation is shown in figure 11.23.
In the example in figure 11.23, H'0008 is set in GR3D, H'0002 is set in GR3A, GR3B, and GR3C, and channel 3 is
activated; then, during operation, H'0000 is set in GR3A, GR3B, and GR3C, and output is performed to external pins
TIOA3 to TIOC3. Note that 0% duty output is not possible even though H'0000 is set.
Pφ
TCNT3
Clock
TCNT3 0008
0000
0001
0002
0003
0007
0008
0000
0001
0002
0003
0004
0005
GR3D
GR3A 3C
(pulse width)
TIO3A
TIO3C
TSR3
0008
0002
0008
Rewritten by software
0000
Cleared by software
Cleared by software
Figure 11.23 Channel 3 to 5 PWM Mode Operation
11.3.11 Event Count Function and Event Cycle Measurement
Channel 9 has six 8-bit event counters (ECNT9A to ECNT9F) and corresponding general registers (GR9A to GR9F). Each
event counter has an external pin (TI9A to TI9F).
Each ECNT9 operates unconditionally as an event counter. When an edge is input from the external pin, ECNT9 is
incremented. When ECNT9 matches the value set in GR9, it is cleared, and then counts up when an edge is again input at
the external pin. By making the appropriate setting in the interrupt enable register (TIER) beforehand, an interrupt request
can be sent to the CPU on compare-match.
For ECNT9A to ECNT9D, a trigger can be transmitted to channel 3 when a compare-match occurs. In channel 3, if the
channel 9 trigger input is set in the timer I/O control register (TIOR) and the corresponding bit is set to 1 in the timer start
register (TSTR), the TCNT3 value is captured in the corresponding general register (GR3A to GR3D) when an ECNT9A
to ECNT9D compare-match occurs. This enables the event cycle to be measured.
An example of event count operation is shown in figure 11.24. In this example, ECNT9A counts up on both-edge, falling-
edge, and rising-edge detection, H'10 is set in GR9A, and a compare-match is generated.
An example of event cycle measurement operation is shown in figure 11.25. In this example, GR3A in channel 3 captures
TCNT3 in response to a trigger from channel 9.
Rev.3.00 Mar. 12, 2008 Page 292 of 948
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