SH7059 Datasheet, PDF (168/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Interrupt Controller (INTC)
7.1.2 Block Diagram
Figure 7.1 is a block diagram of the INTC.
IRQOUT
NMI
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Input
control
CPU/
DMAC
request
judg-
ment
Priority
ranking
judg-
ment
Com-
parator
UBC
H-UDI
DMAC
ATU-II
CMT
A/D
MTAD
SCI
SSU
WDT
HCAN-II
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
ICR
ISR
IPR
IPRA–IPRL
Interrupt
request
SR
I3 I2 I1 I0
CPU
Module bus
Bus
interface
INTC
Legend:
UBC:
H-UDI:
DMAC:
ATU-II:
CMT:
A/D:
MTAD:
User break controller
High-perfotmance user debug
interface
Direct memory access controller
Advanced timer unit-II
Compare match timer
A/D converter
Multi trigger A/D
SCI:
Serial communication interface
SSU:
Synchronous serial communication unit
WDT:
Watchdog timer
HCAN-II: Controller area network-II
ICR:
Interrupt control register
ISR:
IRQ status register
IPRA–IPRL: Interrupt priority level setting registers A to L
SR:
Status register
Figure 7.1 INTC Block Diagram
Rev.3.00 Mar. 12, 2008 Page 78 of 948
REJ09B0177-0300