SH7059 Datasheet, PDF (572/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
17.7.8 Interrupt Sources
Table 17.10 lists the HCAN-II interrupt sources. These sources can be masked using the mailbox interrupt mask register
(MBIMR) and interrupt mask register (IMR). For details on the interrupt vector of each interrupt source, see section 7,
Interrupt Controller (INTC) .
Table 17.10 Interrupt Sources
Interrupt Vector
HCAN0 HCAN1 Description
Interrupt Flag (IRR Bit)
ERS0 ERS1 Error passive interrupt (TEC ≥ 128 or REC ≥ 128)
IRR5
Bus off interrupt (TEC ≥ 256)/bus off recovery (receives IRR6
11 recessive bits 128 times)
Error warning interrupt (TEC ≥ 96)
IRR3
Error warning interrupt (REC ≥ 96)
IRR4
OVR0 OVR1 Reset processing interrupt by power-on reset
IRR0
Overload frame transmission
IRR7
Unread message overwrite/overrun
IRR9
Cycle counter overflow
IRR10
TCMR2 compare match
IRR11
Detection of CAN bus operation in HCAN-II sleep mode IRR12
Timer overrun
IRR13
TCMR0 compare match
IRR14
TCMR1 compare match
IRR15
RM0 RM1 Data frame reception
IRR1
Remote frame reception
IRR2
SLE0 SLE1 Mailbox empty
IRR8
DMAC Activation
HCAN0 HCAN1
Not
Not
possible possible
Possible
Not
possible
Rev.3.00 Mar. 12, 2008 Page 482 of 948
REJ09B0177-0300