SH7059 Datasheet, PDF (431/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Watchdog Timer (WDT)
When a WDT overflow reset is generated simultaneously with a reset input at the RES pin, the RES reset takes priority,
and the WOVF bit in RSTCSR is cleared to 0.
The following registers are not initialized by a WDT reset signal:
• PFC (pin function controller) registers
• I/O port registers
These registers are initialized only by an external power-on reset.
TCNT
value
H'FF
Overflow
H'00
Time
WT/IT = 1
TME = 1
H'00 written
in TCNT
WOVF = 1 WT/IT = 1
TME = 1
WDTOVF and
internal reset generated
H'00 written
in TCNT
WDTOVF
signal
Internal
reset signal*
128 φ clock cycles
Legend:
WT/IT: Timer mode select bit
TME: Timer enable bit
512 φ clock cycles
Note: * Internal reset signal occurs only when the RSTE bit is set to 1.
Figure 13.4 Operation in Watchdog Timer Mode
Rev.3.00 Mar. 12, 2008 Page 341 of 948
REJ09B0177-0300