SH7059 Datasheet, PDF (286/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
• Bits 6 to 4—I/O Control 1B2 to 1B0, 1D2 to 1D0, 1F2 to 1F0, 1H2 to 1H0 (IO1B2 to IO1B0, IO1D2 to IO1D0, IOF12
to IO1F0, IO1H2 to IO1H0): These bits select the general register (GR) function.
Bit 6:IO1x2
0
Bit 5:IO1x1
0
1
1
0
1
Note: x = B, D, F, or H
Bit 4:IO1x0
0
1
0
1
0
1
0
1
Description
GR is an output
compare register
GR is an input
capture register
Compare-match disabled; pin output
undefined
(Initial value)
0 output on GR compare-match
1 output on GR compare-match
Toggle output on GR compare-match
Input capture disabled (GR cannot be written
to)
Input capture in GR on rising edge at TIO1x
pin (GR cannot be written to)
Input capture in GR on falling edge at TIO1x
pin (GR cannot be written to)
Input capture in GR on both rising and falling
edges at TIO1x pin (GR cannot be written to)
• Bit 3—Reserved: This bit is always read as 0. The write value should always be 0.
• Bits 2 to 0—I/O Control 1A2 to 1A0, 1C2 to 1C0, 1E2 to 1E0, 1G2 to 1G0 (IO1A2 to IO1A0, IO1C2 to IO1C0,
IO1E2 to IO1E0, IO1G2 to IO1G0): These bits select the general register (GR) function.
Bit 2:IO1x2
0
Bit 1:IO1x1
0
1
1
0
1
Note: x = A, C, E, or G
Bit 0:IO1x0
0
1
0
1
0
1
0
1
Description
GR is an output
compare register
GR is an input
capture register
Compare-match disabled; pin output
undefined
(Initial value)
0 output on GR compare-match
1 output on GR compare-match
Toggle output on GR compare-match
Input capture disabled
Input capture in GR on rising edge at TIO1x
pin (GR cannot be written to)
Input capture in GR on falling edge at TIO1x
pin (GR cannot be written to)
Input capture in GR on both rising and falling
edges at TIO1x pin (GR cannot be written to)
Rev.3.00 Mar. 12, 2008 Page 196 of 948
REJ09B0177-0300