SH7059 Datasheet, PDF (427/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Watchdog Timer (WDT)
13.1.4 Register Configuration
Table 13.2 summarizes the three WDT registers. They are used to select the clock, switch the WDT mode, and control the
reset signal.
Table 13.2 WDT Registers
Address
Name
Abbreviation
R/W
Initial Value
Write*¹
Read*²
Timer control/status register TCSR
R/(W)*³ H'18
H'FFFFEC10
H'FFFFEC10
Timer counter
TCNT
R/W
H'00
H'FFFFEC11
Reset control/status register RSTCSR
R/(W)*³ H'1F
H'FFFFEC12
H'FFFFEC13
Notes: In register access, four cycles are required for both byte access and word access.
1. Write by word transfer. These registers cannot be written in bytes or longwords.
2. Read by byte transfer. These registers cannot be read in words or longwords.
3. Only 0 can be written to bit 7 to clear the flag.
13.2 Register Descriptions
13.2.1 Timer Counter (TCNT)
TCNT is an 8-bit readable/writable upcounter. (TCNT differs from other registers in that it is more difficult to write to.
See section 13.2.4, Register Access, for details.) When the timer enable bit (TME) in the timer control/status register
(TCSR) is set to 1, the watchdog timer counter starts counting pulses of an internal clock selected by clock select bits 2 to
0 (CKS2 to CKS0) in TCSR. When the value of TCNT overflows (changes from H'FF to H'00), a watchdog timer
overflow signal (WDTOVF) or interval timer interrupt (ITI) is generated, depending on the mode selected in the WT/IT
bit in TCSR.
TCNT is initialized to H'00 by a power-on reset, in hardware and software standby modes, and when the TME bit is
cleared to 0.
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
13.2.2 Timer Control/Status Register (TCSR)
The timer control/status register (TCSR) is an 8-bit readable/writable register. (TCSR differs from other registers in that it
is more difficult to write to. See section 13.2.4, Register Access, for details.) TCSR performs selection of the timer counter
(TCNT) input clock and mode.
TCSR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode.
Bit:
7
6
5
4
3
OVF
WT/IT
TME
–
–
Initial value:
0
0
0
1
1
R/W: R/(W)*
R/W
R/W
R
R
Note: * The only operation permitted on the OVF bit is a write of 0 after reading 1.
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
Rev.3.00 Mar. 12, 2008 Page 337 of 948
REJ09B0177-0300