SH7059 Datasheet, PDF (142/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

3. Floating-Point Unit (FPU)
3.2.3 Floating-Point Status/Control Register (FPSCR)
This LSI has a floating-point status/control register (FPSCR) that functions as a system register accessed by means of LDS
and STS instructions (figure 3.2). FPSCR can be written to by a user program. This register is part of the process context,
and must be saved when the context is switched. It may also be necessary to save this register when a procedure call is
made.
FPSCR is a 32-bit register that controls the storage of detailed information relating to the rounding mode, asymptotic
underflow (denormalized numbers), and FPU exceptions. The module stop bit that disables the FPU itself is provided in
the module standby control register (MSTCR). For details, see section 27, Power-Down State. After a reset start, the FPU
is enabled.
Table 3.1 shows the flags corresponding the five kinds of FPU exception. A sixth flag is also provided as an FPU error
flag that indicates an floating-point unit error state not covered by the other five flags.
Table 3.1 Floating-Point Exception Flags
Flag
E
V
Z
O
U
I
Meaning
FPU error
Invalid operation
Division by zero
Overflow (value not expressed)
Underflow (value not expressed)
Inexact (result not expressed)
Support in this LSI
—
Yes
Yes
—
—
—
The bits in the cause field indicate the exception cause for the instruction executing at the time. The cause bits are
modified by a floating-point instruction. These bits are set to 1 or cleared to 0 according to whether or not an exception
state occurred during execution of a single instruction.
The bits in the enable field specify the kinds of exception to be enabled, allowing the flow to be changed to exception
processing. If the cause bit corresponding to an enable bit is set by the currently executing instruction, an exception
occurs.
The bits in the flag field are used to keep a tally of all exceptions that occur during a series of instructions. Once one of
these bits is set by an instruction, it is not reset by a subsequent instruction. The bits in this field can only be reset by the
explicit execution of a store operation on FPSCR.
Rev.3.00 Mar. 12, 2008 Page 52 of 948
REJ09B0177-0300