SH7059 Datasheet, PDF (502/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Synchronous Serial Communication Unit (SSU)
Start initialization
Clear TE and RE bits in SSER to 0
[1]
Set PFC register
[2]
Specify CSS1, CSS0, MSS, SOL,
and SCKS bits in SSCRH
[3]
Specify bits DATS1 and DATS0
in SSCRL
[4]
Specify CKS2 to CKS0, MLS, CPOS,
and CPHS bits in SSMR
[5] Simultaneously set bits TE, RE, TEIE,
TIE, RIE, and CEIE in SSER
[1] Set up pins SSCK, SSI, and SSO for use as
inputs or outputs.
[2] Specify master, SSO pin output value selection,
SSCK output selection, and SCS pin selection.
[3] Specify transmit/receive data length.
[4] Specify MSB first/LSB first selection, clock
polarity selection, clock phase selection,
and communication clock rate selection.
[5] Specify enable/disable of interrupt request
to the CPU.
End
Figure 16.4 Example of SSU Initialization
• Data Transmission
Figure 16.5 shows an example of transmission operation, and figure 16.6 shows an example of data transmission
flowchart.
When transmitting data, the SSU operates as shown below.
Writing transmit data to SSTDR after the TE bit is set to 1 clears the TDRE bit to 0, and the SSTDR contents is transferred
to SSTRSR. After that, the SSU sets the TDRE bit to 1 and starts transmission. At this time, if the TIE bit in SSER is set to
1, a TXI interrupt is generated.
When 1-frame data has been communication with the TDRE bit cleared to 0, the SSTDR contents are transferred to
SSTRSR to start the next transmission. When the 8th bit of transmit data has been transferred with the TDRE bit set to 1,
the TEND bit in SSSR is set to 1 and the state is retained. At this time, if the TEIE bit is set to 1, a TEI interrupt is
generated. After transmission, the output level of the SSCK pin is fixed at a high level when CPOS = 0 and at a low level
when CPOS = 1.
While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit is cleared to 0.
Rev.3.00 Mar. 12, 2008 Page 412 of 948
REJ09B0177-0300