SH7059 Datasheet, PDF (508/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Synchronous Serial Communication Unit (SSU)
16.4.6 SCS Pin Control and Conflict Errors
When bits CSS1 and CSS0 in SSCRH are specified to 10 is specified to 0, the SCS pin functions as an input (high
impedance) to detect conflict errors. Conflict errors are detected until a serial communication starts from the MSS bit in
SSCRH is set to 1 and after the communication ends. When a low level signal is input on the SCS pin within the conflict
errors detection period, a conflict error occurs. At this time, the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0.
Note: While the CE bit is set to 1, communication is not resumed. Clear the CE bit to 0 before resuming communication.
In addition, set SRES in SSCRL to 1 to reset the internal sequencer and make the initial settings shown in figure
16.4.
External input to SCS
Internal-clocked SCS
MSS
Internal communication
enable signal
CE
SCS output
(Hi-Z)
Data written
to SSTDR
Conflict errors
detection period
Worst time for SCS
internal synchronization
Figure 16.10 Conflict Errors Detection Timing (Before Communication)
φ
SCS
(Hi-Z)
MSS
Internal communication
enable signal
CE
Communication
end
Conflict errors detection period
Figure 16.11 Conflict Errors Detection Timing (After Communication End)
Rev.3.00 Mar. 12, 2008 Page 418 of 948
REJ09B0177-0300