SH7059 Datasheet, PDF (561/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Peripheral data bus
Step 1
ICR0-buf
ICR0_cc
ICR0_tm
17. Controller Area Network-II (HCAN-II)
Peripheral data bus
Step 2
ICR0-buf
ICR0_cc
ICR0_tm
• Write operation for ICR0_cc, ICR0_buf, and ICR0_tm
Write data to the input capture double-buffer (ICR0_buf).
Then write data to the input capture register (ICR0_tm). (The value of the input capture double-buffer (ICR0_buf) is
written to ICR0_cc simultaneously.)
Peripheral data bus
Peripheral data bus
Step 1
ICR0-buf
Step 2
ICR0-buf
ICR0_cc
ICR0_tm
ICR0_cc
ICR0_tm
• ICR1 n (n = 0, 1)
ICR1 records the timestamp for messages to be transmitted and received. Bit 13 (for reception) and bit 12 (for
transmission) in TCR control at which point the timestamp should be recorded. The difference to ICR0 is that ICR1 cannot
be disabled so that the timestamps recorded on messages are always correct.
• ICR0_cc/ICR0_buf
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICR0_cc[3:0]/
ICR0_buf[3:0]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R
R
R
R
R
R
R
R
R
R
R
R R/W* R/W* R/W* R/W*
Bit
Bit Name Initial Value R/W Description
15 to 4 —
0
R
Reserved
The write value should be 0. The read value is not guaranteed.
3
ICR0_cc 0
2
[3:0]/
0
ICR0_buf
1
[3:0]
0
0
0
R/W* This register samples the value of the cycle counter register (CCR) at every
R/W* ^{SOF on the CAN bus when enabled by TCR[14].}
R/W*
R/W*
Note: * This register can be written to, however, the written value is ignored.
Rev.3.00 Mar. 12, 2008 Page 471 of 948
REJ09B0177-0300