SH7059 Datasheet, PDF (612/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Multi-Trigger A/D Converter (MTAD)
19.2.2 A/D Trigger Status Registers 0 and 1 (ADTSR0 and ADTSR1)
A/D trigger status registers 0 and 1 (ADTSR0 and ADTSR1) indicate the compare match generation and the multi-trigger
A/D conversion status in channels 0 and 1.
ADTSR0 and ADTSR1 are initialized to H'00 by a power-on reset, and in hardware standby mode and software standby
mode.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
—
TADFxB TADFxA ADDFxB ADDFxA ADCYLFx ADCMFxB ADCMFxA
0
0
0
0
0
0
0
0
—
R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Note: x = 0 or 1.
* Only 0 can be written, to clear the flag.
• Bit 7—Reserved: This bit is always read as 0. The write value should always be 0.
• Bit 6—Trigger A/D Flag B (TADFxB): Indicates the end of multi-trigger A/D conversion B.
Bit 6: TADFxB
0
1
Note: x = 0 or 1.
Description
Indicates that the multi-trigger A/D converter is performing A/D conversion B, or the
converter is in the idle state
(Initial value)
[Clearing condition]
When TADFxB is read while set to 1, then 0 is written to TADFxB
Indicates that the multi-trigger A/D converter has finished A/D conversion B, and the digital
value has been transferred to ADDR
[Setting condition]
When multi-trigger A/D conversion B ends
• Bit 5—Trigger A/D Flag A (TADFxA): Indicates the end of multi-trigger A/D conversion A.
Bit 5: TADFxA
0
1
Note: x = 0 or 1.
Description
Indicates that the multi-trigger A/D converter is performing A/D conversion A, or the
converter is in the idle state
(Initial value)
[Clearing condition]
When TADFxA is read while set to 1, then 0 is written to TADFxA
Indicates that the multi-trigger A/D converter has finished A/D conversion A, and the digital
value has been transferred to ADDR
[Setting condition]
When multi-trigger A/D conversion A ends
Rev.3.00 Mar. 12, 2008 Page 522 of 948
REJ09B0177-0300