SH7059 Datasheet, PDF (559/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
17.6.8 Cycle Counter Double-Buffer Register n (CCR_buf n) (n = 0, 1)
The cycle counter double-buffer register (CCR_buf) is a 4-bit readable/writable register that is used when the cycle
counter (CCR) and timer counter (TCNTR) are read from or written to simultaneously to refer the same basic cycle
constantly. (This register is used as a temporary retain register to prevent the 20-bit counter value from being updated in
CPU access.)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR_buf[3:0]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R/W R/W R/W R/W
Bit
15 to 4
3 to 0
Bit Name
—
CCR_buf
[3:0]
Initial Value R/W
0
R
0
R/W
Description
Reserved
Cycle Counter Double-Buffer
A temporary retain buffer when accessing the basic cycle of the matrix cycle
for timer triggered transmission (CCR) and timer counter (TCNTR)
simultaneously. The CCR_buf value indicates the same value as write/read
data to/from CCR.
The procedure for accessing the cycle counter (CCR) and timer counter (TCNTR) using the cycle counter double-buffer
(CCR_buf) is described below.
• Read operation
Read the timer counter (TCNTR). (The value of the cycle counter (CCR) is written to the cycle counter double-buffer
(CCR_buf) simultaneously.)
Then read the cycle counter double-buffer (CCR_buf).
Peripheral data bus
Peripheral data bus
Step 1
CCR- buf
Step 2
CCR- buf
CCR
TCNT R
CCR
TCNT R
• Write operation
Write data to the cycle counter double-buffer (CCR_buf).
Then write data to the timer counter (TCNTR). (The value of the cycle counter double-buffer (CCR_buf) is written to the
cycle counter (CCR) simultaneously.)
Peripheral data bus
Peripheral data bus
Step 1
CCR- buf
CCR- buf
Step 2
CCR
TCNT R
CCR
TCNT R
Rev.3.00 Mar. 12, 2008 Page 469 of 948
REJ09B0177-0300