SH7059 Datasheet, PDF (164/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

6. Exception Processing
6.6 When Exception Sources Are Not Accepted
When an address error or interrupt is generated after a delayed branch instruction or interrupt-disabled instruction, it is
sometimes not accepted immediately but stored instead, as shown in table 6.10. When this happens, it will be accepted
when an instruction that can accept the exception is decoded.
Table 6.10 Generation of Exception Sources Immediately after a Delayed Branch Instruction or Interrupt-
Disabled Instruction
Exception Source
Point of Occurrence
Bus Error
Interrupt
FPU Exception
Immediately after a delayed branch instruction^*1
Not accepted
Not accepted
Not accepted
Immediately after an interrupt-disabled instruction^*2
Not accepted^*4
Not accepted
Accepted
Immediately after an FPU instruction^*3
Not accepted
Not accepted
Accepted
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF
2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L
3. FPU instructions: Table 2.18, Floating-Point Instructions, and table 2.19, FPU-Related CPU Instructions, in
section 2.4.1, Instruction Set by Classification.
4. In the SH-2 a bus error is accepted.
Rev.3.00 Mar. 12, 2008 Page 74 of 948
REJ09B0177-0300