SH7059 Datasheet, PDF (350/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
11.2.15 Free-Running Counters (TCNT)
The free-running counters (TCNT) are 32- or 16-bit up- or up/down-counters. The ATU-II has 17 TCNT counters: one 32-
bit TCNT in channel 0, and sixteen 16-bit TCNTs in each of channels 1 to 7 and 11. For details of the channel 10 free-
running counters, see section 11.2.26, Channel 10 Registers.
Channel
0
1
2
3
4
5
6
7
11
Abbreviation
TCNT0H, TCNT0L
TCNT1A, TCNT1B
TCNT2A, TCNT2B
TCNT3
TCNT4
TCNT5
TCNT6A–D
TCNT7A–D
TCNT11
Function
32-bit up-counter (initial value H'00000000)
16-bit up-counters (initial value H'0000)
16-bit up/down-counters (initial value H'0001)
16-bit up-counters (initial value H'0001)
16-bit up-counter (initial value H'0000)
Free-Running Counter 0 (TCNT0H, TCNT0L): Free-running counter 0 (comprising TCNT0H and TCNT0L) is a 32-bit
readable/writable register that counts on an input clock. The counter is started when the corresponding bit in the timer start
register (TSTR1) is set to 1. The input clock is selected with prescaler register 1 (PSCR1).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
When TCNT0 overflows (from H'FFFFFFFF to H'00000000), the OVF0 overflow flag in the timer status register (TSR0)
is set to 1.
TCNT0 can only be accessed by a longword read or write. Word reads or writes should not be used.
TCNT0 is initialized to H'00000000 by a power-on reset, and in hardware standby mode and software standby mode.
Free-Running Counters 1A, 1B, 2A, 2B, 3, 4, 5, 11 (TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4,
TCNT5, TCNT11): Free-running counters 1A, 1B, 2A, 2B, 3, 4, 5, and 11 (TCNT1A, TCNT1B, TCNT2A, TCNT2B,
TCNT3, TCNT4, TCNT5, TCNT11) are 16-bit readable/writable registers that count on an input clock. Counting is started
when the corresponding bit in the timer start register (TSTR1 or TSTR3) is set to 1. The input clock is selected with
prescaler register 1 (PSCR1) and the timer control register (TCR).
Rev.3.00 Mar. 12, 2008 Page 260 of 948
REJ09B0177-0300