SH7059 Datasheet, PDF (495/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Synchronous Serial Communication Unit (SSU)
16.3.5 SS Status Register (SSSR)
SSSR is a status flag register for interrupts.
Bit:
7
6
5
—
ORER
—
Initial value:
0
0
0
R/W: R/W
R/(W)*
R/W
Note: * Write 0 to clear the flag.
4
3
2
1
0
—
TEND
TDRE
RDRF
CE
0
0
1
0
0
R/W
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Bit Bit Name Initial Value R/W Description
7
⎯
0
⎯
Reserved
These bits are always read as 0. The write value should always be 0.
6
ORER
0
R/W Overrun Error
If the next data is received while RDRF = 1, an overrun error occurs,
indicating abnormal termination. SSRDR stores 1-frame receive data
before an overrun error occurs and loses data received later. While ORER
= 1, continuous serial reception cannot be continued. Serial transmission
cannot be continued, either.
[Setting condition]
• When the next reception data is transferred to SSRDR while RDRF = 1
[Clearing condition]
• When 0 is written to ORER after reading ORER = 1
5, 4 ⎯
All 0
⎯
Reserved
These bits are always read as 0. The write value should always be 0.
3
TEND
0
R
Transmit End
[Setting condition]
• When the last bit of transmit data is transmitted with TDRE = 1
[Clearing conditions]
• When 0 is written to the TEND bit after reading TEND = 1
• When data is written to SSTDR
2
TDRE
1
R/W Transmit Data Empty
Indicates whether or not SSTDR contains transmit data.
[Setting conditions]
• When the TE bit in SSER is 0
• When data is transferred from SSTDR to SSTRSR and SSTDR is ready
to be written to.
[Clearing conditions]
• When 0 is written to the TDRE bit after reading TDRE = 1
• When data is written to SSTDR with TE = 1
Rev.3.00 Mar. 12, 2008 Page 405 of 948
REJ09B0177-0300