SH7059 Datasheet, PDF (242/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Direct Memory Access Controller (DMAC)
10.4 Examples of Use
10.4.1 Example of DMA Transfer between On-Chip SCI and External Memory
In this example, on-chip serial communication interface channel 0 (SCI0) receive data is transferred to external memory
using DMAC channel 0.
Table 10.5 indicates the transfer conditions and the set values of each of the registers.
Table 10.5 Transfer Conditions and Register Set Values for Transfer between On-chip SCI and External Memory
Transfer Conditions
Transfer source: RDR0 of on-chip SCI0
Transfer destination: external memory
Transfer count: 64 times
Transfer source address: fixed
Transfer destination address: incremented
Transfer request source: SCI0 (RDR0)
Bus mode: cycle-steal
Transfer unit: byte
Interrupt request generation at end of transfer
DMAC master enable on
Register
SAR0
DAR0
DMATCR0
CHCR0
DMAOR
Value
H'FFFFF005
H'00400000
H'00000040
H'00020105
H'0001
10.4.2 Example of DMA Transfer between A/D Converter and On-Chip Memory (Address Reload On)
In this example, on-chip A/D converter channel 0 is the transfer source and on-chip memory is the transfer destination, and
the address reload function is on.
Table 10.6 indicates the transfer conditions and the set values of each of the registers.
Table 10.6 Transfer Conditions and Register Set Values for Transfer between A/D Converter and On-Chip
Memory
Transfer Conditions
Transfer source: on-chip A/D converter ch1 (A/D1)
Transfer destination: on-chip memory
Transfer count: 128 times (reload count 32 times)
Transfer source address: incremented
Transfer destination address: incremented
Transfer request source: A/D converter ch1 (A/D1)
Bus mode: burst
Transfer unit: byte
Interrupt request generation at end of transfer
DMAC master enable on
Register
SAR2
DAR2
DMATCR2
CHCR2
DMAOR
Value
H'FFFFF820
H'FFFF6000
H'00000080
H'010C110D
H'0001
Rev.3.00 Mar. 12, 2008 Page 152 of 948
REJ09B0177-0300