SH7059 Datasheet, PDF (505/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Synchronous Serial Communication Unit (SSU)
(1) When 8-bit data length is selected (SSRDR0 is valid) with CPOS = 0 and CPHS = 0
SCS
1 frame
1 frame
SSCK
SSI
RDRF
Bit Bit Bit Bit Bit Bit Bit Bit
01234567
SSRDR0 (LSB first transmission)
Bit Bit Bit Bit Bit Bit Bit Bit
76543210
SSRDR0 (MSB first transmission)
LSI operation
User operation
Dummy-read
SSRDR0
RXI
interrupt
generated
Read SSRDR0
RXI
interrupt
generated
(2) When 16-bit data length is selected (SSRDR0 and SSRDR1 are valid) with CPOS = 0 and CPHS = 0
SCS
1 frame
SSCK
SSI
(LSB first)
SSI
(MSB first)
RDRF
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
0123456776543210
SSRDR1
SSRDR0
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
76543210 01234567
SSRDR0
SSRDR1
LSI operation
User operation _Dummy-read
SSRDR0, SSRDR1
RXI
interrupt
generated
(3) When 32-bit data length is selected (SSRDR0 and SSRDR3 are valid) with CPOS = 0 and CPHS = 0
SCS
SSCK
SSI
(LSB first)
SSI
(MSB first)
RDRF
Bit
0
to
Bit Bit
70
to
Bit Bit
70
to
Bit
7
Bit
0
to
Bit
7
SSRDR3
SSRDR2
SSRDR1
SSRDR0
Bit _to Bit Bit _to Bit Bit _to Bit Bit _to Bit
7
07
07
07
0
SSRDR0
SSRDR1
SSRDR2
SSRDR3
LSI operation
User operation _Dummy-read
SSRDR0, SSRDR1,
SSRDR2, SSRDR3
RXI
interrupt
generated
Figure 16.7 Example of Reception Operation
Rev.3.00 Mar. 12, 2008 Page 415 of 948
REJ09B0177-0300