SH7059 Datasheet, PDF (496/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Synchronous Serial Communication Unit (SSU)
Bit Bit Name Initial Value R/W Description
1
RDRF
0
R/W Receive Data Register Full
Indicates whether or not SSRDR contains received data.
[Setting condition]
• When receive data is transferred from SSTRSR to SSRDR after
successful data reception
[Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When received data is read from SSRDR
0
CE
0
R/W Conflict Error
Indicates that a conflict error has occurred when 0 is externally input via the
SCS pin with MSS = 1.
Serial receive operation cannot continue if CE has been set to 1.
Furthermore, serial transmit operation cannot continue. Before restarting
communication, do not fail to set SRES in SSCRL to 1 to reset the internal
sequencer and make the initial settings shown in figure 16.4.
[Setting condition]
• When a low level is input to the SCS pin in master device mode (MSS in
SSCRH = 1)
[Clearing condition]
• When 0 is written to the CE bit after reading CE = 1
SSSR is initialized by a power-on reset, hardware standby mode, and software standby mode. It is not initialized by a
manual reset.
Rev.3.00 Mar. 12, 2008 Page 406 of 948
REJ09B0177-0300