SH7059 Datasheet, PDF (390/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
11.4 Interrupts
The ATU has 75 interrupt sources of five kinds: input capture interrupts, compare-match interrupts, overflow interrupts,
underflow interrupts, and interval interrupts.
11.4.1 Status Flag Setting Timing
IMF (ICF) Setting Timing in Input Capture: When an input capture signal is generated, the IMF bit and ICF bit are set
to 1 in the timer status register (TSR), and the TCNT value is simultaneously transferred to the corresponding GR, ICR,
and OSBR.
The timing in this case is shown in figure 11.37.
In the example in figure 11.37, a signal is input from an external pin, and input capture is performed on detection of a
rising edge.
CK
Input capture input
Internal input capture
signal
TCNT
t_TICS (input capture input setup time)
N
GR (ICR)
N
Interrupt status flag
IMF (ICF)
Interrupt request signal
IMI (ICI)
Figure 11.37 IMF (ICF) Setting Timing in Input Capture
IMF (ICF) Setting Timing in Compare-Match: The IMF bit and CMF bit are set to 1 in the timer status register (TSR)
by the compare-match signal generated when the general register (GR) output compare register (OCR), or cycle register
(CYLR) value matches the timer counter (TCNT) value. The compare-match signal is generated in the last state of the
match (when the matched TCNT count value is updated).
The timing in this case is shown in figure 11.38.
Rev.3.00 Mar. 12, 2008 Page 300 of 948
REJ09B0177-0300