SH7059 Datasheet, PDF (222/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Direct Memory Access Controller (DMAC)
10.2 Register Descriptions
10.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3)
Bit:
31
30
29
28
27
26
25
24
Initial value:
—
—
—
—
—
—
—
—
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
23
22
21
…
…
Initial value:
—
—
—
…
R/W:
R/W
R/W
R/W
…
…
2
1
0
…
…
—
—
—
…
R/W
R/W
R/W
DMA source address registers 0–3 (SAR0–SAR3) are 32-bit readable/writable registers that specify the source address of
a DMA transfer. These registers have a count function, and during a DMA transfer, they indicate the next source address.
Specify a 16-bit boundary when performing 16-bit data transfers, and a 32-bit boundary when performing 32-bit data
transfers. Operation cannot be guaranteed if any other addresses are set.
The initial value after a power-on reset and in standby mode is undefined.
10.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3)
Bit:
31
30
29
28
27
26
25
24
Initial value:
—
—
—
—
—
—
—
—
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
23
22
21
…
…
Initial value:
—
—
—
…
R/W:
R/W
R/W
R/W
…
…
2
1
0
…
…
—
—
—
…
R/W
R/W
R/W
DMA destination address registers 0–3 (DAR0–DAR3) are 32-bit readable/writable registers that specify the destination
address of a DMA transfer. These registers have a count function, and during a DMA transfer, they indicate the next
destination address.
Specify a 16-bit boundary when performing 16-bit data transfers, and a 32-bit boundary when performing 32-bit data
transfers. Operation cannot be guaranteed if any other addresses are set.
The value after a power-on reset and in standby mode is undefined.
Rev.3.00 Mar. 12, 2008 Page 132 of 948
REJ09B0177-0300