SH7059 Datasheet, PDF (11/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

SH7058 (Rev.3, REJ09B0046-0300H)
2.5.1 State Transitions
Figure 2.8 Transitions between Processing States
59
From any state
when RES = 0
and HSTBY = 1
Power-on reset state
RES = 0
HSTBY = 1
When an interrupt source
or DMA address error occurs
RES = 1
Exception processing state
Bus request
cleared
Bus request
generated
Bus release state
Exception
processing
source occurs
NMI interrupt
source occurs
Exception
processing
ends
Bus request
generated
Bus request
cleared
Bus request
generated
Bus request
cleared
SBY bit
cleared
for SLEEP
instruction
Program execution state
SBY bit set
for SLEEP
instruction
Differences between SH7058 and SH7058S/SH7059
SH7058S/SH7059
2.5.1 State Transitions
Figure 2.8 Transitions between Processing States
Figure amended
From any state
when RES = 0
and HSTBY = 1
Power-on reset state
When an interrupt source
or DMA address error occurs
RES = 1
Exception processing state
RES = 0
HSTBY = 1
NMI pin
0 →1
Bus request
cleared
Bus request
generated
Bus release state
Exception
processing
source occurs
Exception
processing
ends
Bus request
generated
Bus request
cleared
Bus request
generated
Bus request
cleared
SBY bit
cleared
for SLEEP
instruction
Program execution state
SBY bit set
for SLEEP
instruction
Sleep mode
Software standby mode
Hardware standby mode
Sleep mode
Software standby mode
Hardware standby mode
Power-down state
From any state when
RES = 0 and HSTBY = 0
Power-down state
From any state when
RES = 0 and HSTBY = 0
Note: An internal reset due to the WDT causes a transition from the program execution state
or sleep mode to the exception processing state.
5.1 Overview
73
The internal clock signal (φ), with frequency either four or
eight times the frequency of the clock signal input from the
EXTAL pin, is mainly supplied to the bus master modules.
5.1.1 Block Diagram
Figure 5.1 Block Diagram of Clock Pulse Generator
73
XTAL → Oscillator circuit
PLL multiplier circuit → Internal clock (φ)
X 4 or X 8
5.1.2 Pin Configuration
Table 5.1 CPG Pins
74
Pin Name
Abbreviation
Crystal
XTAL
I/O
Input
Note: An internal reset due to the WDT causes a transition from the program execution state
or sleep mode to the exception processing state.
5.1 Overview
Description amended
The internal clock signal (φ), with frequency eight times
the frequency of the clock signal input from the EXTAL pin,
is mainly supplied to the bus master modules.
5.1.1 Block Diagram
Figure 5.1 Block Diagram of Clock Pulse Generator
Figure amended
SYSCR1, Oscillation stop detection circuit, and On-chip
oscillator circuit deleted
XTAL ↔ Oscillator circuit
PLL multiplier circuit → Internal clock (φ)
X8
5.1.2 Pin Configuration
Table 5.1 CPG Pins
Table amended
Pin Name
Crystal
Abbreviation
XTAL
I/O
Input/output
Rev.3.00 Mar. 12, 2008 Page xi of xc
REJ09B0177-0300