SH7059 Datasheet, PDF (870/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

25. ROM (SH7059)
Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other
chips for which the history of erasure is unknown, auto-erasing as a check and supplement for the initialization
(erase) level is recommended.
2. Automatic programming to a single address block can only be performed once. Additional programming to an
address block that has already been programmed is not allowed.
25.10 Further Information
25.10.1 Serial Communication Interface Specification for Boot Mode
Initiating boot mode enables the boot program to communicate with the host by using the on-chip SCI. The serial
communication interface specifications are shown below.
• Status
The boot program has three states.
(1) Bit-rate-adjustment state
In this state, the boot program adjusts the bit rate to communicate with the host. Initiating boot mode enables starting
of the boot program and entry to the bit-rate-adjustment state. The program receives the command from the host to
adjust the bit rate. After adjusting the bit rate, the program enters the inquiry/selection state.
(2) Inquiry/Selection state
In this state, the boot program responds to inquiry commands from the host. The device name, clock mode, and bit
rate are selected. After selection of these settings, the program is made to enter the programming/erasing state by the
command for a transition to the programming/erasing state. The boot program transfers the erasure program to RAM
and erases the user MATs and user boot MATs before the transition.
(3) Programming/erasing state
Programming and erasure by the boot program take place in this state. The boot program is made to transfer the
programming/erasing program to RAM by commands from the host. Checksums and blank checks are executed by
sending these commands from the host.
These boot program states are shown in figure 25.26.
Rev.3.00 Mar. 12, 2008 Page 780 of 948
REJ09B0177-0300