SH7059 Datasheet, PDF (76/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 4 Operating Modes .............................................................................................................. 57
4.1 Operating Mode Selection ..................................................................................................................................... 57
Section 5 Clock Pulse Generator (CPG) .......................................................................................... 59
5.1 Overview................................................................................................................................................................ 59
5.1.1 Block Diagram.......................................................................................................................................... 59
5.1.2 Pin Configuration...................................................................................................................................... 60
5.2 Frequency Ranges.................................................................................................................................................. 60
5.2.1 Frequency Ranges..................................................................................................................................... 60
5.3 Clock Source.......................................................................................................................................................... 61
5.3.1 Connecting a Crystal Oscillator ................................................................................................................ 61
5.3.2 External Clock Input Method.................................................................................................................... 62
5.4 Usage Notes ........................................................................................................................................................... 63
Section 6 Exception Processing........................................................................................................ 65
6.1 Overview................................................................................................................................................................ 65
6.1.1 Types of Exception Processing and Priority ............................................................................................. 65
6.1.2 Exception Processing Operations.............................................................................................................. 66
6.1.3 Exception Processing Vector Table .......................................................................................................... 66
6.2 Resets ..................................................................................................................................................................... 68
6.2.1 Types of Reset .......................................................................................................................................... 68
6.2.2 Power-On Reset ........................................................................................................................................ 68
6.2.3 Manual Reset ............................................................................................................................................ 69
6.3 Address Errors ....................................................................................................................................................... 70
6.3.1 Address Error Sources .............................................................................................................................. 70
6.3.2 Address Error Exception Processing......................................................................................................... 70
6.4 Interrupts................................................................................................................................................................ 71
6.4.1 Interrupt Sources....................................................................................................................................... 71
6.4.2 Interrupt Priority Level ............................................................................................................................. 71
6.4.3 Interrupt Exception Processing ................................................................................................................. 72
6.5 Exceptions Triggered by Instructions .................................................................................................................... 72
6.5.1 Types of Exceptions Triggered by Instructions ........................................................................................ 72
6.5.2 Trap Instructions ....................................................................................................................................... 72
6.5.3 Illegal Slot Instructions ............................................................................................................................. 73
6.5.4 General Illegal Instructions....................................................................................................................... 73
6.5.5 Floating-Point Instructions........................................................................................................................ 73
6.6 When Exception Sources Are Not Accepted ......................................................................................................... 74
6.7 Stack Status after Exception Processing Ends ....................................................................................................... 75
6.8 Usage Notes ........................................................................................................................................................... 75
6.8.1 Value of Stack Pointer (SP) ...................................................................................................................... 75
6.8.2 Value of Vector Base Register (VBR) ...................................................................................................... 75
6.8.3 Address Errors Caused by Stacking of Address Error Exception Processing........................................... 76
Section 7 Interrupt Controller (INTC).............................................................................................. 77
7.1 Overview................................................................................................................................................................ 77
7.1.1 Features..................................................................................................................................................... 77
7.1.2 Block Diagram.......................................................................................................................................... 78
7.1.3 Pin Configuration...................................................................................................................................... 79
7.1.4 Register Configuration.............................................................................................................................. 79
7.2 Interrupt Sources.................................................................................................................................................... 80
7.2.1 NMI Interrupts .......................................................................................................................................... 80
7.2.2 User Break Interrupt ................................................................................................................................. 80
Rev.3.00 Mar. 12, 2008 Page lxxvi of xc
REJ09B0177-0300