SH7059 Datasheet, PDF (183/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7.4.2 Stack after Interrupt Exception Processing
Figure 7.3 shows the stack after interrupt exception processing.
7. Interrupt Controller (INTC)
Address
4n–8
4n–4
4n
PC*¹
SR
32 bits
32 bits
SP*²
Notes: 1. PC: Start address of the next instruction (return destination instruction)
after the executing instruction
2. Always be certain that SP is a multiple of 4
Figure 7.3 Stack after Interrupt Exception Processing
Rev.3.00 Mar. 12, 2008 Page 93 of 948
REJ09B0177-0300